Design Framework to Build Next-Generation Analog Computing Chipsets

IISc researchers have created a design framework for the creation of next-generation analog computing chipsets, which may operate faster and with less power than the digital chips used in the majority of electronic devices.

ARYABHAT-1 Chip Micrograph. Image Credit: NeuRonICS Lab, DESE, Indian Institute of Science.

The group has created a prototype of an analog chipset called ARYABHAT-1 (Analog Reconfigurable technologY And Bias-scalable Hardware for AI Tasks) using their innovative design framework. This kind of chipset can be particularly useful for Artificial Intelligence (AI)-based applications like object or speech recognition—like Alexa or Siri—or those that call for highly efficient massively parallel computations.

Digital chips are used in the majority of electronic devices, especially those that involve computing, because the design process is straightforward and scalable.

But the advantage of analog is huge. You will get orders of magnitude improvement in power and size.

Chetan Singh Thakur, Assistant Professor, Department of Electronic Systems Engineering (DESE), Indian Institute of Science

The development of the analog chipset is being spearheaded by Chetan Singh Thakur’s lab. Analog computing has the potential to perform better than digital computing in applications that do not call for precise calculations because the former is more energy-efficient.

When designing analog chips, there are several technological challenges to overcome. Analog processor testing and co-design are challenging, in contrast to digital chips. By compiling a high-level code, it is simple to create large-scale digital processors, and the same design can be transferred with little modification between different technology development generations, such as from a 7 nm chipset to a 3 nm chipset.

The design of analog chips is costly because they are difficult to scale and require individual customization when moving to new applications or the next generation of technology. Another difficulty with analog design is that it is difficult to trade off power and area for accuracy and speed.

In digital design, precision can be increased by simply adding more logic units to the same chip, and the power at which they function can be changed without impairing the functionality of the device.

The team has created a novel framework that enables the creation of analog processors that scale similarly to digital processors to overcome these difficulties. Their chipset can be modified and programmed so that the same analog modules can be used in various applications and process design generations.

You can synthesize the same kind of chip at either 180 nm or at 7 nm, just like digital design.

Chetan Singh Thakur, Assistant Professor, Department of Electronic Systems Engineering (DESE), Indian Institute of Science

The researchers claim that ARYABHAT can be used to program various machine learning architectures that, like digital processors, can function reliably in a wide range of temperatures. They continue by stating that the architecture is also “bias-scalable,” meaning that even when the operating conditions, such as voltage or current, change, its performance does not.

This means that the same chipset can be set up for both high-speed tasks like object detection and Internet of Things (IoT) applications that require extremely low energy consumption.

The design framework was created by Pratik Kumar, a Ph.D. student at IISc, in conjunction with Shantanu Chakrabartty, a professor at Washington University in St. Louis’ (WashU) McKelvey School of Engineering and WashU’s McDonnell Academy ambassador to IISc.

It’s good to see the theory of analog bias-scalable computing being manifested in reality and for practical applications.

Shantanu Chakrabartty, Professor, Washington University in St. Louis

Chakrabartty had earlier proposed bias-scalable analog circuits.

Two pre-print studies that are undergoing peer review present the findings of the researchers. Additionally, they have applied for patents, and they intend to collaborate with business partners to commercialize the technology.

Source: https://iisc.ac.in/

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